同上一篇一样，也是做过的实验 ，这里只发一个顶层文件给大家，提供一个整体的思路，因为整个设计包括比较多的vhdl文件，所以不便于上传，

----------the clock top design file
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity clock is
  port(clk_20m : in std_logic;----20M晶振输入
    rst : in std_logic;----复位按钮(总清0)
       clk_dis : in std_logic;---扫描频率
    --clk_con : in std_logic;---总控制台计数频率
  alarm_set : in std_logic;
    choose_mode : in std_logic;---先择12小时制(0)还是24小时制(1)
       set_min : in std_logic;--设置分的单脉冲发生器
       set_hou : in std_logic;---设置小时的单脉冲发生器
    display7 : out std_logic_vector(6 downto 0);--7个数码管的公共的7端
    select6 : out std_logic_vector(5 downto 0);--6个片选端
    alarm : out std_logic);---闹钟输出
end entity clock;
------------------------------------------------
architecture behave of clock is
signal clk_1s : std_logic;
signal second_l,second_h : std_logic_vector(3 downto 0);
signal minute_l,minute_h : std_logic_vector(3 downto 0);
signal hour_l,hour_h : std_logic_vector(3 downto 0);
signal carry_clk1,carry_clk2,carry_clk3 : std_logic;
signal decoder_temp : std_logic_vector(3 downto 0);
signal lock_temp : std_logic;
signal reg_temp1,reg_temp2 : std_logic_vector(3 downto 0);
signal reg_temp3,reg_temp4 : std_logic_vector(3 downto 0);
component division is---------division modul
 generic (data : integer);
 port(clk_in : in std_logic;
   clk_out : out std_logic);
end component;
component count10 is---------------count10
 port(clk1 : in std_logic;
   clr1 : in std_logic;
   carry1 : out std_logic;
   value1 : out std_logic_vector(3 downto 0));
end component;
component count6 is-----------------count6;
 port(clk2 : in std_logic;
   clr2 : in std_logic;
   carry2 : out std_logic;
   value2 : out std_logic_vector(3 downto 0));
end component;
component reg is-----------------------reg;
  port(lock : in std_logic;
       DataIn0,DataIn1 : in std_logic_vector(3 downto 0);
  DataIn2,DataIn3 : in std_logic_vector(3 downto 0);
  DataOut0,DataOut1 : out std_logic_vector(3 downto 0);
  DataOut2,DataOut3 : out std_logic_vector(3 downto 0));
end component reg;
component timing is--------------------timing
 port(clr_time : in std_logic;
  setclk_h : in std_logic;
  setclk_m : in std_logic;
  select12_24 : in std_logic;--'0'==12   '1'==24
  data_min_l : out std_logic_vector(3 downto 0);--分的低位
  data_min_h : out std_logic_vector(3 downto 0);--分的高位
  data_hou_l : out std_logic_vector(3 downto 0);--小时的低位
  data_hou_h : out std_logic_vector(3 downto 0));--小时的高位
end component timing;
component scan is------------------------scan
  port(clk_scan : in std_logic;
     data0,data1,data2 : in std_logic_vector(3 downto 0);
        data3,data4,data5 : in std_logic_vector(3 downto 0);
  dataout : out std_logic_vector(3 downto 0);
  choose : out std_logic_vector(5 downto 0));
end component;
component decoder7s is-----------------decoder
 port(binary : in std_logic_vector(3 downto 0);
      bcd : out std_logic_vector(6 downto 0));
end component decoder7s;
-----------------进行元件例化
 begin
U1: division generic map(data => 20000000)
   port map(clk_20m,clk_1s);
U2: count10 port map(clk_1s,rst,carry_clk1,second_l);
U3: count6 port map(carry_clk1,rst,carry_clk2,second_h);
U4: timing port map(rst,set_hou,set_min or carry_clk2,choose_mode,minute_l,minute_h,hour_l,hour_h);
--U5: timing port map(rst,control_temp,set_hou,carry_clk2,choose_mode,minute_l,minute_h,hour_l,hour_h);
U6: scan port map(clk_dis,second_l,second_h,minute_l,minute_h,hour_l,hour_h,decoder_temp,select6);
U7: decoder7s port map(decoder_temp,display7);
U8: reg port map(lock_temp,minute_l,minute_h,hour_l,hour_h,reg_temp1,reg_temp2,reg_temp3,reg_temp4);
P1: process(clk_20m,alarm_set)
  begin
  if alarm_set='1' then lock_temp <= '1';
  else lock_temp <= '0';
  end if;
 end process;
P4: process(clk_20m,lock_temp)
 begin
 if reg_temp1=minute_l and reg_temp2=minute_h and reg_temp3=hour_l and reg_temp4 = hour_h then
  alarm <= '1';
 end if;
 end process;
end architecture;

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